The present invention relates generally to manufacture of semiconductor devices incorporating a metal interconnect. More specifically, it relates to compositions and processes to remove post etch residues, photoresists and other polymers at an interconnect level, such as with a copper metallurgy, preferably incorporating a damascene/dual damascene structure. The invention also relates to a flexible remover chemistry that can be used in such damascene/dual damascene processes, as well as for other remover applications, such as aluminum, or aluminum alloy interconnects with misarranged tungsten plugs.
Today's 0.18 μm technology is reaching hole dimensions of 0.25 μm. Since the introduction of 0.25 μm technology, interconnects are becoming the limiting speed factor of the device due to interconnect resistively as well as the RCA delay induced by adjacent interconnects. This is expected to continue with feature sizes decreasing further in the manometer ranges (e.g., 65 nm devices). More recently developed interconnects use copper as the conducting material and low-k or ultra low-k dielectric material (a dielectric, having a dielectric constant smaller than the dielectric constant of silicon dioxide, e.g., porous low-k dielectrics). Copper has been selected due to its lower resistance than aluminum interconnects. Similarly, another way to achieve reduced capacitance between adjacent metal lines is to decrease the dielectric constant of the material in-between the lines. Accordingly, the industry has been introducing a variety of new low-k and ultra low-k materials. A key challenge in reduced geometry devices, such as 0.18 μm technology, is the interconnect RC delay time, which becomes the limiting factor of the device performance. This delay can be improved by combining low and ultra low k dielectrics as better insulators and the use of copper as a better conductor. The demand for faster devices and continued reduction is device size has required the use of different processing approaches to accommodate the materials.
Copper has been chosen because it is a relatively inexpensive metal with better conductivity (ρ=1.7 Ωcm) than aluminum (ρ=2.7 Ωcm). However the main drawbacks of this material are (1) its high diffusivity into silicon, introducing risk of a “device-killing” defect in the front end device, and (2) the difficulty of dry etching copper containing metallurgies and integrating such metals in traditional processes. Copper does not form an oxide passivation layer under ambient conditions (as aluminum does), making this metal very difficult to work with.
Since copper can not easily be dry etched, the use of damascene or dual damascene structures have emerged to integrate copper containing materials as, for example, interconnects in semiconductor devices. The emergence of dual damascene processes, combined with the appearance of a variety of new materials such as organic polymers for low-k and ultra low-k inter metal dielectric material, and the need to etch complex layers of dielectric materials, photoresist removal and cleaning steps require a new strategic approach.
Dual damascene structures are the easiest way to introduce copper containing metallurgies and have the advantage of incorporating both lines and vias in one deposition step; this reduces the number of process steps and is therefore cost effective. Variations of the dual damascene structure exist, incorporating a series of layers for process purposes such as anti-reflective coatings, adhesion promoters, moisture barriers, diffusion barriers, polishing stops, buried etch mask and so on. The choice of whether those have to be used or not and what material (SiOxNy or Six Ny) should be used for them often depend upon the final choice of the low-k or ultra low-k material.
Due to the variety and complexity of the process and materials such as the choice of dielectric, stripping and cleaning is a critical step in the dual damascene process. In particular, it is important to inhibit infiltration into and contamination of the low-k and ultra low-k material due to back sputtering, which can change k values. The typical location of such is on the sidewalls of trench and via features, where low-k and ultra low-k properties are particularly important. Therefore, it is desirable to have a flexible remover that can effectively remove copper containing materials, such as residues and remaining polymer, that could lead to such infiltration and contamination on the sidewalls of the trench and via.
During the fabrication of microcircuits, photoresist material is used to pattern, and transfer patterns onto the appropriate material. For example at interconnect levels the appropriate material will be either metal for electrically conducting paths or dielectric for isolating material in-between the conducting lines.
FIGS. 1 and 2 show a typical structure used in this case. To integrate copper and eventually aluminum, the pattern is transferred from the photoresist (3) through the dielectric (2). The gaps are then filled up by the conducting layer. This process is called damascene and can integrate either one level of interconnect only (single damascene) or both the horizontal interconnects and the vertical interconnects called vias (dual damascene). Vias always open atop the underlying metal lines (1) and good cleanliness of the via is required in order to minimize electrical resistance along the interconnect.
Various processes have been developed to build those structures, as disclosed, for example, in U.S. Pat. Nos. 5,739,579; 5,635,423; 5,705,430 and 5,686,354, which can include optional layers into the dielectric stack (5, 6) but all such processes have in common:                that the via needs to be cleaned of all post etch residues (7 and 8), without damaging the metal, before the second metal layer can be deposited,        that the whole dielectric material needs to be cleaned of copper compounds back-sputtered onto the sidewall and top surface (8) on the underlying copper during the final part of the etching, called “opening”.        that remaining polymer, such as photoresist or other gap-fill polymer or sacrificial polymer needs to be effectively removed prior to filling the trench and via with copper.        
Accordingly, IC manufacturing requires the excellent cleaning of copper residues, as copper diffuses very easily into silicon dioxide and other dielectric materials ultimately risking the creation of a failure (“killing” the device) and effective removal of polymer and photoresist. It is further advantageous if one chemistry can be used in all applications while simultaneously avoiding unacceptable etching of the copper substrate.
It has been described previously to clean materials used in the semiconductor industry by including a small amount (generally between 1% and 5% weight) of choline and other compounds to remove or avoid adsorption of metal impurities (U.S. Pat. Nos. 4,239,661, 4,339,340, PAJ 6,163,495, PAJ 6,041,773, PAJ 2,275,631, PAJ 1,191,450). Choline base is also well known for its use as developer of positive working photoresist (U.S. Pat. Nos. 4,294,911, 4,464,461). It has also been recognized that choline base can act as a etching agent of metal for thin film layer definition (PAJ 62,281,332, U.S. Pat. No. 4,172,005) and that adding choline atoms into an etching chamber when etching copper helps to lower the process temperature and hence minimize copper oxidation. U.S. Pat. No. 5,846,695 discloses aqueous solutions of quaternary ammonium hydroxides, including choline, in combination with nucleophilic amines and sugar and/or sugar alcohols, for removal of photoresist and photoresist residues in integrated circuit fabrication. However, U.S. Pat. No. 5,846,695 requires sugar and/or sugar alcohols to prevent corrosion while the present invention is sugar and/or sugar alcohol free while still providing low rates of corrosion.
In addition, the formulations of the present invention effectively remove polymers, such as photoresist, antireflective coatings and gap-fill or sacrificial polymers, in addition to cleaning residues left after etching dielectric material and openings to the copper layer. Those residues can be minimal if the main etching residues and photoresist are cleaned/stripped before the final step of forming openings on copper—if an etch stop layer is used, in which case the residues are due to the “opening” etch step only, e.g. copper rich residues on the bottom of the openings and copper back sputtered onto the dielectric material surfaces. But the residues become more complex if the “opening” etch is done directly after the main etch or if the process does not use an etch stop layer and the opening etch is done simultaneously with opening the via—in a trench first dual damascene process. In that case, the post etch treatment is required to clean main etch residues (containing CFx, CHFx . . . ), to clean the bottom residues (containing Cu, CuO, CuO2), as well as the back sputtered copper and polymer remaining post etch in either or both the via or the trench.
Existing wet remover, stripping and cleaning compositions used in the semiconductor industry are not suitable in such situations for the following reasons:                traditional amine-containing chemistries are not compatible with copper and dissolve the metal at the exposed areas;        the variety of low-k and ultra low-k dielectrics used combined with continuing demands in performance and reductions of size (e.g., to nanometer ranges) requires a remover that has both broader range of application without a loss of effectiveness as a remover.        acidic chemistries, such as dilute hydrofluoric acid solutions (DHF), have caused problems in unwantedly changing the designed dimentions of the device by aggressively attacking the sidewall of the dielectric. Furthermore those solutions are ineffective for cleaning Cu2O or CFx compounds, typically found in back-sputtered residues and as contamination to dielectric materials and such chemistries do not effectively dissolve remaining polymers and photoresists, such as acrylate and methacrylate polymers transparent in lithography <250 nm, which after processing steps, leading to the need for supplemental remover steps, such as dry removal techniques, such as oxygen plasma ashing.        
Oxygen plasma ashing of remaining polymers and photoresists is not ideal in dual damascene processes and introduces additional problems, for example:                an oxygen plasma step can oxidize exposed copper to the CuO and Cu2O states, which will increase the via resistance, and        an oxygen plasma step can damage exposed organic dielectric material by etching the material in an uncontrolled manner, potentially compromising the integrity of the circuit.        
Regarding the dielectric, the industry's choice of low-k and ultra low-k dielectric material has yet to emerge, though various candidates have been suggested. It has been shown that a general trend to achieve lower dielectric constant uses less silicon and more carbon, often introducing voids. There is then a logical evolution from the inorganic materials (such as SiO2 [∈=4], SiOF [∈=3.5]) to silsesquioxane types of material (such as HSQ, MSQ [3.0<∈<3.5]), towards organic material, such as benzyl cyclobutane (BCB) or silicon low k (SiLK) [∈=2.7]), achieving lower k values with air gaps.
Further, in certain dual damascene processes, e.g., via first, a crown or fence may be created on the top of the trench after the etch process which is difficult to remove. Dry techniques such as ashing will not remove the fence or the crown, making it desirable to have a remover that can effectively remove the fence or crown residue.
With the use of low-k and ultra low-k dielectrics, which may be porous, the use of trench-first dual damascene processes become more attractive to avoid contamination in the via caused by residual photoresist that may be absorbed by the dielectric during the trench formation in a via-first dual damascene process, altering the k value of the dielectric. Where a trench-first process is used, a sacrificial polymer layer may be used to protect the dielectric side walls during the formation of the via.
The exemplary descriptions presented herein describe a means to overcome the potential problems and disadvantages faced in a dual damascene process, such as the aforementioned low-k and ultra low-k dielectric contamination. In addition, the exemplary descriptions provide a process and chemistry to overcome potential problems in trench first dual damascene processing, such as preventing the oxidation of the copper metal due to, for example, the use of an oxygen plasma. The exemplary description introduces a flexible chemistry that can be used at several steps in the dual damascene process to remove photoresists and other polymers, while at the same time removing etch residues, simplifying the dual damascene process.